a boring simulation of a logo a photo of the merced dieEPIC/IA64 support for GCC

Last change: 2000-01-06


The E2k and Merced will ship sometime in 2000 or 2001. With them comes a new technology, not CISC nor RISC nor even VLIW - but EPIC!

While individual key concepts (predication, speculative loads and explicit parallelisation) are no new inventions, EPIC is the first architecture making use of all of them in a unique way.

The first EPIC chip that was announced, the Merced, will be based on the IA64 instruction set architecture, jointly developed by HP and Intel. Recently another EPIC chip, the E2k from Elbrus, was announced that might get delivered much earlier than the Merced, much pricier and just as fast. Production might start as early as Q4 2000.

Since it's a new technology, GCC, my favourite compiler, does not yet support it. This has to be changed.....

What you will find here

At the moment, you will find links to articles having more information on EPIC (including IA64 and Merced), as well as references to research literature.

If you want to join the development effort (or have additional information), just contact the EPIC mailinglist <epic@gcc.za.org>. If you want to get subscribed to it, ask Marc Lehmann <pcg@goof.com> (the list is currently managed manually).

Links

Related projects

Related Software

Our work

Our data directory

Papers/Books not publicly available online

Here are some research papers and books on predication and VLIW. Do not bother to look for them online, unless you have ACM or IEEE online access to their biblios.

If you find any of these documents online, please send me the link!

%A Wenn-Mei Hwu
%T Introduction to Predicated Execution
%J IEEE Computer
%D January 1998
%X Short explanation of predicated execution and if-conversion

%A Wen-Mei Hwu
%A Richard E. Hank
%A David M. Gallagher
%A Scott A. Mahlke
%A Daniel M. Lavery
%A Grant E. Haab
%A John C. Gyllenhaal
%A David I. August
%T Compiler Technology for Future Microprocessors
%J Proceedings of the IEEE
%V 83
%N 12
%D December 1995
%X Detailed explanation of predication and if-conversion. Results on spec cint92 and spec cfp92

%A Kemal Ebcioglu
%A Randy D. Groves
%A Ki-Chang Kim
%A Gabriel M. Silberman
%A Isac Ziv
%T VLIW Compilation Techniques in a Superscalar Environment
%J ACM SIGPLAN 94-6
%C Orlando, Florida, USA
%D 1994
%K global scheduling, software pipelining, VLIW superscalars
%X Description of speculative load/store motion out of loops, unspeculation, scheduling, limited combining and basic block expansion.

%A Monica Lam
%T Software Pipelining: an Effective Scheduling Technique for VLIW Machines
%J ACM SIGPLAN 88
%C Atlanta, Georgia
%D June 22-24 1988
%X Comparison with trace scheduling. Results on the WARP machine for Livermore Loops.

%A Utpal Banerjee
%A Rudolf Eigenmann
%A Alexandru Nicolau
%A David A. Padua
%T Automatic Program Parallelization
%J Proceedings of the IEEE
%V 81
%N 2
%D February 1993
%X Describes (among other methods): trace scheduling and percolation scheduling.

%A B. R. Rau et al.
%T The Cydra 5 Departmental Supercomputer
%J IEEE Computer
%D January 1989
%P 12-35
%X Cydra is one of the first VLIW machines.

%A Lowney
%T The Multiflow Trace Scheduling
%J Journal of Supercomputing
%D May 1993
%X Multiflow is one of the first VLIW machines.

%A J. A. Fisher
%T Very Long Instruction Word Architectures and the ELI-512
%J Proceedins of the 10th Symposium on Computer Architectures
%E ACM Press
%P 140-150
%C NY
%D 1983
%X Fisher done pioneer work on VLIW's.

For additional questions/comments/critics do not hesitate to drop me a line!
Marc Lehmann <pcg@goof.com>